This invention is related in general to the field of electrical and electronic circuits. More particularly, the invention is related to a fast saturation recovery operational amplifier input stage.
The advancement of communication technology is pushing higher demands for faster and better behaved circuits. For operational amplifiers, the demand is for larger bandwidths and faster slew rates. As circuit speed increases, circuit design becomes even more challenging. With faster circuit speeds, parasitic capacitances become a critical component in determining the transient and frequency response of the circuit.
Traditionally, operational amplifier differential input pairs undergo saturation during fast slewing conditions. One side of the differential pair turns off while the other side slews at full power. The faster the edge speed of the input signal and the higher the bandwidth of the operational amplifier, the deeper into saturation the operational amplifier input transistor sinks. Once the operational amplifier input transistor is done with slewing, it is difficult to transition from saturation to the high gain region and settling to within the operational amplifier open loop accuracy. Therefore, the deep saturation of the input transistor increases the transient time for the operational amplifier to go into the high gain region. The problem shows up as a poor settling behavior after the rising and/or falling edges of high speed input signals.
Traditionally, this problem is mitigated by providing significantly larger amounts of quiescent current through the operational amplifier when compared with the total current needed during the slewing conditions. This solution is disadvantageous because it requires much higher power consumption. Other approaches have added slew compensation networks that are too complex and therefore is inadequate for high speed applications. Yet other approaches use simplistic slew compensation networks that provide uncontrolled amounts of current that are either insufficient or excessive. Still other approaches, such as one described in chapter 6 of Johns, D., Analog Integrated Circuit Design, published by John Wiley and Sons, Inc. 1997, where the added measures are not sufficient or too slow to react when the input has a high frequency waveform in high speed communications applications.
Accordingly, there is a need for an input stage of the operational amplifier to be saturation-free during slewing conditions and to be able to respond quickly to high speed differential input waveforms.
In accordance with the present invention, an anti-saturation operational input stage is provided which eliminates or substantially reduces the disadvantages associated with prior circuits.
In one aspect of the invention, an operational amplifier input stage includes a differential input pair receiving a differential input voltage, and a translinear loop circuit coupled to the differential input pair operable to supply an instantaneous current to the differential input pair sufficient to charge capacitances in the differential input pair during slewing conditions.
In another aspect of the invention, an operational amplifier input stage includes a first differential input transistor and a second differential input transistor receiving a differential input voltage. A first translinear loop is coupled to the first differential input transistor and a second translinear loop is coupled to the second differential input transistor. The first and second translinear loops are operable to supply an instantaneous current to the respective first and second differential input transistors to sufficiently charge capacitances therein during slewing conditions.
In yet another aspect of the invention, an operational amplifier having a folded cascode input stage includes a first differential input transistor and a second differential input transistor receiving a differential input voltage, a first translinear loop coupled to the first differential input transistor and a second translinear loop coupled to the second differential input transistor, the first and second translinear loops operable to supply an instantaneous current to the respective first and second differential input transistors to sufficiently charge capacitances therein during slewing conditions. Each of the translinear loop includes a first current source transistor with its emitter coupled to the collector of the first differential input transistor and its collector coupled to an active load circuit, a second current source transistor with its emitter coupled to the emitter of the first current source transistor and the collector of the first differential input transistor and operable to supply current to the first differential input transistor to prevent the first differential input transistor from going into saturation during slewing conditions, and to supply current to the first current source transistor to prevent the first current source transistor from turning off during slewing conditions, a first biasing circuit coupled to the second current source transistor operable to supply a first fixed bias voltage therefor, and a second biasing circuit coupled to the first current source transistor operable to supply a second fixed bias voltage therefor, the second fixed bias voltage having a fixed relationship with the first fixed bias voltage.